The present invention relates to semiconductor devices and their methods of fabrication. More particularly, the present invention relates to the processing of calcium-copper alloy interconnect material and the resultant device utilizing the same. Even more particularly, the present invention relates to reducing and minimizing carbon, sulphur, and oxygen impurities in a calcium-copper alloy interconnect surface.
Currently, the semiconductor industry is demanding faster and denser devices (e.g., 0.05-xcexcm to 0.25-xcexcm) which implies an ongoing need for low resistance metallization. Such need has sparked research into resistance reduction through the use of barrier metals, stacks, and refractor metals. Despite aluminum""s (Al) adequate resistance, other Al properties render it less desirable as a candidate for these higher density devices, especially with respect to its deposition into plug regions having a high aspect ratio cross-sectional area. Thus, research into the use of copper (Cu) as an interconnect material has been revisited, copper being advantageous as a superior electrical conductor, providing better wettability, providing adequate electromigration resistance, and permitting lower depositional temperatures. Cu interconnect material may be deposited by CVD, PECVD, sputtering, electroless plating, and electrolytic plating. However, some disadvantages of using Cu as an interconnect material include etching problems, corrosion, and diffusion into silicon. These problems have sparked further research into the formulation of barrier materials for Cu, which in turn, identified another host of problems associated with the barrier materials themselves (e.g., contamination).
In response to interconnect impurity level concerns relating to the fabrication of semiconductor devices having copper (Cu) alloy interconnect surfaces, the industry has been utilizing chemical vapor deposition (CVD) methods. Ca is an inherently highly reactive element in air; therefore, Cuxe2x80x94Ca alloys would behave similarly. Contamination in the Cuxe2x80x94Ca alloys is especially problematic when wet-chemical methods are used for processing. Cuxe2x80x94Ca alloy surfaces have been found to be highly susceptible to carbon (C), sulphur (S), and oxygen (O) contamination, forming an impure layer on the order of 10-20 xc3x85 in thickness, as
1Peter Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, 3rd Ed., p. 397 (1997). characterized by AES/XPS methods. However, although CVD has been conventionally used for depositing other metal(s) on an interconnect surface, CVD is not a cost-effective method of doping Cu interconnect surfaces with Ca ions. Therefore, a need exists for providing a method of fabricating a semiconductor device having contaminant-reduced Caxe2x80x94Cu alloy on Cu interconnect surfaces by cost-effectively removing the contaminant layer. 
Accordingly, the present invention provides a method of fabricating a semiconductor device having contaminant-reduced Caxe2x80x94Cu alloy surfaces formed on Cu interconnects by cost-effectively removing the contaminant layer and a device thereby formed. Contaminant removal from a Cuxe2x80x94Caxe2x80x94X surface, where contaminant Xxe2x95x90C, S, or O, is achieved by sputtering the Cuxe2x80x94Caxe2x80x94X surface in an Ar atmosphere between the steps of (a) immersing the Cu interconnect surface into an electroless plating solution comprising Cu salts, Ca salts, their complexing agents, a reducing agent, a pH adjuster, and at least one surfactant for facilitating Ca-doping of the Cu interconnect material; and (b) annealing of the Caxe2x80x94Cu alloy surface onto the underlying Cu interconnect material to form a Caxe2x80x94Cu/Cu interconnect structure, whereby the sputtering step, under argon (Ar), selectively and effectively removes contaminants from the Cuxe2x80x94Caxe2x80x94X layer containing higher concentrations of C, S, or O, thereby minimizing the post-annealed contaminant level, and thereby producing a uniform Caxe2x80x94Cu alloy surface (i.e., Cu-rich with 0.2-5% Ca) on the Cu interconnect material for maximizing Caxe2x80x94Cu/Cu interconnect structure reliability, electromigration resistance, and corrosion prevention. The annealing step primarily removes O and secondarily removes C and S, especially when performed under vacuum, an inert gas, or a reducing ambient such as ammonia (NH3) plasma. Thus, the resultant device then comprises a distinctive contaminant-reduced Caxe2x80x94Cu/Cu interconnect structure.